1. Field of the Invention
The present invention relates to an active type solid-state imaging device using a metal-oxide-semiconductor field-effect transistor (hereinafter, referred to as "MOSFET") or a junction gate FET. More particularly, the present invention relates to an active type solid-state imaging device which can realize an excellent performance and a lower driving voltage.
2. Description of the Related Art
An active type solid-state imaging device has been proposed as a replacement for a currently used imaging device using a charge-coupled device (CCD). In the active type solid-state imaging device, signal charges generated in respective pixels are not read out by themselves, but are read out by a scanning circuit after the signal charges have been amplified in the respective pixels. Such a device eliminates the limit on the signal magnitude and makes a dynamic range broader than that of Et CCD type imaging device. Moreover, in such a device, since the signal charges are read out by driving the pixels to be read out only in a horizontal and perpendicular line with a lower voltage, a smaller amount of power consumption is required than that of a CCD type imaging device.
In such a device, a transistor is generally employed to amplify the signal charges in a pixel; an SIT type, a bipolar type, an FET type (an MOS type or a junction type), and the like have been proposed. Since it is generally easier to employ MOSFETs in a scanning circuit, considering the configuration of the device, it is more advantageous to use FET type pixels. More preferably, it is advantageous to use a device in which only a single FET is contained inside a pixel in order to increase the pixel density. A charge modulation device (CMD) type, a floating gate array (FGA) type, and a bulk charge modulation device (BCMD) type have been reported as active type imaging devices.
FIGS. 12A and 12B show CMD type pixels of a conventional active type solid-state imaging device, in which a plurality of pixels are arranged in a matrix. FIG. 12A is a plan view of the pixels, and FIG. 12B is a cross-sectional view taken along a line 12B--12B in FIG. 12A. FIG. 13 shows a potential distribution in a perpendicular direction taken along a line 13--13 in FIG. 12B. The active type solid-state imaging device shown in these figures is described in Nakamura et al., "Gate-accumulation type MOS phototransistor image sensor", 1986 Television Academy, p. 57. As is apparent from FIG. 12B, an n-well 2 is formed as a buried channel in a p-substrate 1. A gate electrode 3 is formed on the n-well 2 with an insulating film 6 therebetween. A source region 4 and a drain region 5, composed of a highly-concentrated n-layer and separated by the n-well 2, are formed in the n-well 2. As shown in FIG. 12A, the gate electrodes 3 of the respective pixels are connected in common to gate terminals 7 in a horizontal direction, and the respective source regions 4 are connected in common to source terminals 8 in a vertical direction.
An operation of the CMD type pixel will be described with reference to FIG. 13. First, at the time of signal accumulation, a gate voltage is set to be a voltage V.sub.L and signal charges (holes) generated by photoelectric conversion are accumulated in an interface between the semiconductor and the insulating film. Then, at the time of signal reading, the gate voltage is set to be a voltage V.sub.M, which is a higher potential than the voltage V.sub.L, and a current between the source and the drain regions 4 and 5 varies in accordance with the amount of the signal charges. The varied value of the current is read out as a signal output. The other pixels on the same source terminal 8 are not detected because the gate voltage is in a V.sub.L level. That is, only the selected pixels are read out. At the time of the resetting operation, by which signal charges are cleared to be ready for the next signal accumulation, the gate voltage is set to be a voltage V.sub.H, SO that the potential in the substrate decreases along a direction perpendicular to the substrate. The signal charges (holes) accumulated in the interface between the n-well 2 and the insulating film 6 are then discharged into the substrate 1 under the interface, as shown by the broken lines in FIG. 12B.
A conventional CMD type imaging device has the following shortcomings. First, the gate voltage at the time of the resetting operation must be very high because the concentration of the impurity in the buried n-well channel layer should be set to be high so that the density of the accumulated signal charges may be high. For example, a case of employing the following Condition 1 will be analyzed.
[Condition 1]
Impurity concentration of the substrate: 1.0.times.10.sup.15 cm.sup.-3 PA0 Impurity concentration of the n-layer: 3.0.times.10.sup.15 cm.sup.-3 PA0 Thickness of the n-layer: 1.5 .mu.m PA0 Thickness of the gate insulating film: 80 nm PA0 K.sub.S : S relative dielectric constant PA0 .epsilon..sub.0 : Vacuum dielectric constant PA0 .epsilon.: Elementary electric charge PA0 d.sub.n : X.sub.j (junction depth) of the n-well PA0 Y.sub.FB : Flat band voltage
Using this condition, the condition where the potential decreases linearly from the surface of the n-well 2 to the p-substrate 1 is expressed as follows:
[Equation 1] ##EQU1## N.sub.n : Carrier concentration of the n-well N.sub.p : Carrier concentration of the p-substrate
As a result, the gate voltage V.sub.G required for the resetting operation is 20.0 volts if a flat band voltage V.sub.FB is -0.85 volts; therefore, the gate voltage V.sub.G is an impractical value.
In a conventional CMD type imaging device, another problem occurs because the depletion of the interface between the n-well 2 and the insulating film 6 causes the generation of a considerable dark current.
An FGA type imaging device is employed among the active type solid-state imaging devices of the FET type to reduce the generation of the dark current. FIG. 14A shows a cross-sectional view of an FGA type imaging device. FIG. 14B shows a potential distribution in a direction taken along the line 14B--14B in FIG. 14A. The prior art device shown in these figures is described in J. Hynecek, "A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensor", IEEE Trans. Elec. Dev., p. 646 (1988).
This FGA type imaging device is different from the CMD type imaging device in that a p-layer 9 in a relatively high concentration is provided on the n-well 2 under the gate electrode 3, as shown in FIG. 14A. A gate voltage is set to be V.sub.L at the time of the signal accumulation and the signal reading, and the variation of the channel potential of the n-well 2 is detected as a variation of the threshold value in accordance with the accumulation of the signal charges (holes) in the p-layer 9. The other pixels on the same signal line are not detected because the gate voltage is in a V.sub.L level only at the time of the signal reading.
In this FGA type imaging device, a similar reading operation is conducted to that of the CMD type imaging device, i.e., the gate voltage is set to be V.sub.H which makes a potential in the substrate decrease linearly in a direction perpendicular to the substrate. The signal charges (holes) accumulated in the p-layer 9 are discharged into the substrate 1 under the p-layer 9. According to this structure, the p-layer 9 is not depleted even at the time of the resetting operation, so the generation of the dark current is reduced. However, if the p-layer 9 is not depleted at the time of the resetting operation, the signal charges are not completely transferred. Consequently, the generation of residual images and the increase of resetting noise cannot be prevented.
A BCMD type imaging device is proposed to improve the defects of the FGA type imaging device in J. Hynecek, "BCMD--An Improved Photosite Structure for High Density Image Sensor", IEEE Trans. Elec. Dev., p. 1011 (1991). FIG. 15A shows a cross section of a BCMD type pixel, and FIG. 15B shows a potential distribution in a direction taken along the line 15B--15B in FIG. 15A. As shown in FIG. 15A, in a BCMD type imaging device, a p-layer 11, an n-layer 12, and a p-layer 13 are stacked in this order on an n-substrate 10. P-layers in a high concentration 14 are formed for a source electrode and a drain electrode so as to reach the p-layer 11 through the n-layer 12 and the p-layer 13.
This BCMD type imaging device is different from the FGA type imaging device in the following points:
1) The signal charges are converted into electrons and accumulated in the buried channel n-layer 12.
2) The potential variation of the p-layer 13 caused by the signal charges are detected as a variation of the threshold value of the p-MOS structure.
3) At the time of the resetting operation, the gate voltage is set to be lower (V.sub.L) and the signal charges are discharged into the n-substrate 10.
Accordingly, the complete transfer of the signal charges is accomplished. However, the p-n-p-n multilayered structure of this device makes it difficult to optimize the driving conditions and makes the fabrication steps complicated.
In order to overcome the problems of the above-mentioned respective active type solid-state imaging devices, the applicant of the present application has proposed two kinds of pixels with novel structures in the followings: Japanese Patent Application No. 6-303953 and Japanese Laid-Open Patent Publication No. 8-250697.
FIG. 16 shows a twin gate MOS image sensor (TGMIS) type pixel disclosed in Japanese Patent Application No. 6-303953. A first gate electrode 22 (photo-gate) and a second gate electrode 23 (reset-gate) are formed on a p-type semiconductor substrate 21 with an insulating film 27 therebetween. An n-type semiconductor layer 24 is formed in a surface region of the p-type semiconductor substrate 21 under the first gate electrode 22, and a pair of n.sup.+ diffusion layers are formed in the n-type semiconductor layer 24. One n.sup.+ diffusion layer forms a source region 25 of MOSFET and the other n.sup.+ diffusion layer forms a drain region 26. The first gate electrode 22 works as a gate.
In the above-mentioned structure, light h.upsilon. incident through the first gate electrode 22 generates an electron-hole pair by photoelectric conversion, while the electrons flow into the drain region 26. The holes are collected by a potential barrier formed in the middle of the n-type semiconductor layer 24 and a potential barrier formed under the second gate electrode 23 and turned into the signal charges accumulated in the interface between the insulating layer 27 and the n-type semiconductor layer 24.
The amount of the potential variation in the n-type semiconductor layer 24 in accordance with the amount of the signal charges is detected as a potential variation at the source region 25 and regarded as an output signal. The signal charges are easily discharged along the route shown by the broken line in FIG. 16 into the p-type semiconductor substrate 21 by lowering the potential barrier under the second gate electrode 23. In the structure shown in FIG. 16, a sufficiently large amount of signal charges can be accumulated in the surface region and the resetting operation can be conducted at a low voltage.
In FIG. 16, the reference numeral 32 denotes a first gate region under the first gate electrode 22 of the n-type semiconductor layer 24, and the reference numeral 33 denotes a reset region under the second gate electrode 23.
FIG. 17 shows an image sensor portion A in which pixels shown in FIG. 16 are arranged in matrix. The first gate electrodes 22 are connected in common to a first vertical scanning circuit 40 through clock lines 30 denoted by V.sub.A (i), V.sub.A (i+1), etc. in a horizontal direction in FIG. 17. The second gate electrodes 23 are connected in common to a second vertical scanning circuit 41 through clock lines 31 denoted by V.sub.B (i), V.sub.B (i+1), etc. in a horizontal direction.
The source region 25 is formed per pixel in the middle of the first gate region 32 of the n-type semiconductor layer 24. The source regions 25 are connected in common to signal lines 28 denoted by V.sub.S (j), V.sub.S (j+1), etc. in a column direction of the pixels. The drain regions 26 are formed in the periphery of each pixel as shown by hatched portions and are supplied with a voltage V.sub.D through drain terminals 29 from the periphery thereof.
FIG. 22 shows Bulk Drain MOS Image Sensor (BDMIS) type pixels proposed in Japanese Patent Application No. 7-51641. An n-well 1022 is formed in a p-type semiconductor substrate 1021 so as to be in contact with a surface 1051 of the p-type semiconductor substrate 1021. A p.sup.+ -source 1023 is formed in the n-well 1022 so as to be in contact with the surface 1051. A first gate electrode 1024 is formed on a region of the n-well 1022 excluding the p.sup.+ -source 1023 with an insulating film 1061 formed therebetween. A second gate electrode 1025 is formed on a region of the p-type semiconductor substrate 1021 adjacent to the n-well 1022 with the insulating film 1061 formed therebetween. A portion 1053 in the vicinity of the surface of the n-well 1022, the insulating film 1061, and the first gate electrode 1024 collectively form a first gate region 1055.
A portion 1054 in the vicinity of the surface of the p-type semiconductor substrate 1021, the insulating film 1061, and the second gate electrode 1025 collectively form a second gate region 1056.
When an appropriate voltage is applied to the first gate electrode 1024, a p-channel is formed by minority carriers (holes) in the portion 1053. When an appropriate voltage is applied to the second gate electrode 1025, a p-channel is formed in an entire region of the p-type semiconductor substrate 1021 below the second gate electrode 1025 including the portion 1054. Thus, a channel for allowing an electric current (holes) to flow is formed between the p-type semiconductor substrate 1021 with a voltage V.sub.D applied thereto and the p.sup.+ -source 1023 with a voltage V.sub.S applied thereto. As a result, an electric current flows as represented by a solid line in FIG. 22.
When light h.upsilon. is incident through the first gate electrode 1024, it generates an electron-hole pair by photoelectric conversion in the n-well 1022 positioned below the first gate electrode 1024 and the p-type semiconductor substrate 1021. The generated holes flow into the p.sup.+ -source 1023, while the electrons are collected by a potential barrier formed in the middle of the n-well 1022 and turned into the signal charges. The electrons which are turned into the signal charges are majority carriers in the n-well 1022. The accumulated signal charges vary the potential of the n-well 1022 in accordance with the charge amount, and further vary the surface potential of the portion 1053.
Accordingly, an electric current flowing through the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023 varies in accordance with the amount of the accumulated signal charges. If a constant current is allowed to flow between the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023, an electric potential between the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023 varies in accordance with the amount of the accumulated signal charges. Furthermore, if a constant electric potential is kept between the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023, a current flowing between the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023 varies in accordance with the amount of the accumulated signal charges. In this manner, a first transistor is formed between the p-type semiconductor substrate 1021 and the p.sup.+ -source 1023, using the portions 1053 and 1054 as channels, and the electrical characteristics of the transistor change depending upon the amount of the accumulated signal charges.
Furthermore, a reset drain region 1026 is provided in the p-type semiconductor substrate 1021 in such a manner that the reset drain region 1026 is formed adjacent to the portion 1054 so as to be in contact with the surface 1051. When an appropriate voltage V.sub.B is applied to the second gate electrode 1025 so as to lower a potential barrier of the portion 1054 of the second gate region 1056, the signal charges accumulated in the n-well 1022 flow into the reset drain region 1026 along a route represented by a dotted line in FIG. 22. In this manner, a second transistor is formed between the n-well 1022 and the reset drain region 1026, using the portion 1054 as a channel, whereby signal charges are discharged.
FIG. 23 shows an image sensor portion in which the pixels shown in FIG. 22 are arranged in matrix. The first gate electrodes 1024 are connected in common to a first vertical scanning circuit 40 through clock lines denoted by V.sub.A (i), V.sub.A (i+1), etc. in a horizontal direction in FIG. 23. The second gate electrodes 1025 are connected in common to a second vertical scanning circuit 41 through clock lines denoted by V.sub.B (i), V.sub.B (i+1), etc. in a horizontal direction.
The source region 1023 is formed per pixel at the center of the first gate region 1055 of the n-well 1022. The source regions 1023 are connected in common to signal lines 1034 denoted by V.sub.S (j), V.sub.S (j+1), etc. in a column direction of the pixels. The substrate 1021 is used as a drain region, such that it is not shown in FIG. 23.
FIG. 24 is a cross-sectional view of an active type solid-state imaging device (corresponding to a cross section taken along a line PQR in FIG. 17) in which an image sensor portion A being formed of the TGMIS-type pixels described with reference to FIG. 16 and a driving circuit portion B are provided on a p-type semiconductor substrate 120'.
The portions in the image sensor portion A corresponding to those shown in FIG. 16 are denoted by the reference numerals identical with those of FIG. 16; specific descriptions thereof will be omitted here. The driving circuit portion B corresponds to the second vertical scanning circuit 41 (shown in FIG. 17) composed of a complementary metal oxide semiconductor (CMOS) inverter.
A substrate electric potential V.sub.SUB is supplied to the driving circuit portion B through a p.sup.+ -region 101 formed on the surface of the p-type semiconductor substrate 120'. A well 130 with the same conductivity as that of the p--type semiconductor substrate 120' and a well 140 with the conductivity opposite to that of the p-type semiconductor substrate 120' are formed on the p-type semiconductor substrate 120'. An electric potential V.sub.L is applied to the well 130 through the p.sup.+ -region 131. On the other hand, an electric potential V.sub.H is applied to the well 140 through an n.sup.+ -region 141.
In the case where the active type solid-state imaging device of the TGMIS type is driven, a pulse generated by a vertical scanning circuit for the first gate electrode (photo-gate electrode) has an amplitude of V.sub.L -V.sub.H, and a pulse generated by a vertical scanning circuit for the second gate electrode (reset-gate electrode) has an amplitude of V.sub.M -V.sub.H (V.sub.L .ltoreq.V.sub.M .ltoreq.V.sub.H). Therefore, when the image sensor portion A and the driving circuit portion B are formed on the identical p-type semiconductor substrate, the image sensor portion A is required to be positioned far away from the driving circuit portion B in accordance with the required difference in electric potential. This prevents the improvement of integration and limits the degree of freedom of a driving voltage. Furthermore, when different voltages are set on the identical substrate, even if the image sensor portion A is positioned far away from the driving circuit portion B, an invalid current is generated by the difference in set electric potentials. This also allows a parasitic bipolar transistor or a parasitic thyristor to operate, leading to malfunction.
The above-mentioned problems arise in the TGMIS-type imaging device and the BDMIS-type imaging device, as well as the improved TGMIS-type imaging device. This is because the image sensor portion and the driving circuit portion are formed on the identical semiconductor layer in either of the devices.